1. Technical Field
This invention relates generally to semiconductor integrated circuit devices. More particularly, this invention relates to dry cleaning post metal chemical mechanical polishing of integrated semiconductor devices and the integrated semiconductor devices fabricating therefrom.
2. Related Art
Design improvements are being made for modern families of semiconductor integrated circuits (IC's). An overall size of the IC may be reduced by employing smaller devices that make up the IC as well as layout improvements that provide for tighter packing or increased density of those devices. By increasing the density of the IC, the IC will occupy less space on a die on which the IC is laid out, and therefore, more dies can be cut from a single wafer. Increased density also may result in increased speed of the IC, reduced manufacturing costs for the IC, and reduced costs of equipment employing such an IC.
IC's commonly employ millions to billions of electronic components such as transistors, diodes, conductive interconnecting lines, and resistive and capacitive regions. Multiple IC's may be laid out on a die. Multiple dies may be laid out on the wafer. The IC may include multiple levels of electronic components where a planar interlevel dielectric (ILD) layer is formed between the various levels to electrically isolate the layers and the components therein. A trench may be formed in an ILD to form an interconnect between layers.
A process for planarizing the ILD, referred to as a chemical mechanical polishing (CMP) process, includes using a polishing tool, a pad and a slurry in a sequence of steps to planarize a surface of the wafer and/or to remove undesired materials from the surface of the wafer. The polishing pad is coupled with the polishing tool. The pad is applied to the surface of the wafer. The polishing pad applies the polishing slurry against the surface of the wafer. The pad and slurry are traversed across the surface of the wafer, generally by rotating the pad with respect to the surface of the wafer. The slurry may include polishing agents or chemical abrasives that remove undesired materials from the wafer and form a planar surface.
In a process referred to as a damascene sequence, trenches are etched into a oxide surface to form lines or locations where metal material is desired. The trenched oxide layer may be back-filled with the desired metal material such as tungsten. The trenched oxide layer is filled with the metal material so that the metal material fills the trenches as well as a layer above the oxide layer. The CMP process is used to polish the surface to oxide layer to remove substantially all metal material from the surface of the oxide layer and leaving the metal material substantially only in the trenches. The metal in the trenches forms the metal pattern in the oxide.
A problem with metal CMP processes, for example in the damascene sequence, is the generation of a micro-scratch or a small trench in the surface of the wafer. During the CMP process, the metal material may be smeared into the micro-scratch leaving a residue of metal material in the micro-scratch. The residue of metal material may affect an unintended trench that crosses the metal pattern. The unintended trench may create a short between lines in the metal pattern. The trench also may create leakage currents between components or may cause an early life time failure of the IC. Subsequent processes that address concerns introduced by residue-filled micro-scratches increase the cost of the IC and/or decrease the yield for the IC. Accordingly, there is a need for post metal CMP process to remove residue filled micro-scratches.